Parallel Critic-Free Reinforcement Learning with Direct Parameter Space Mapping for Large-Scale Analog LDO Sizing
Published in IEEE International Symposium on Circuits and Systems (ISCAS), 2025
This paper proposes a parallel critic-free reinforcement learning framework with direct parameter space mapping that achieves significantly faster convergence for large-scale analog LDO circuit sizing optimization.
Recommended citation: Wu, H.*, Jiang, H.*, Wang, Z., An, W., Yuan, B., Lu, Y., & Jiang, J. (2025). "Parallel Critic-Free Reinforcement Learning with Direct Parameter Space Mapping for Large-Scale Analog LDO Sizing." IEEE International Symposium on Circuits and Systems (ISCAS). #